1. Field of the Invention
The present invention relates to a data transmission system, a controller, and its method, particularly to a data transmission system having a transmitter for transmitting a reference signal and a phase modulation signal having the phase difference related to the value of input data from the reference signal and a receiver for obtaining the data in accordance with the phase difference between the reference signal and the phase modulation signal which are received.
2. Related Art
FIG. 7 is an illustration showing a configuration of a data transmission system disclosed in Japanese Patent Laid-Open No. 2003-174484, which has a data transmitter 1 and a data receiver 2. FIG. 8 is an illustration showing a configuration of the data transmitter 1 in FIG. 7. As shown in FIG. 8, the data transmitter 1 has delay circuits 11 and 12 and multiplexers 13 and 14. The multiplexer 13 has inverters 13-1 and 13-2 and NAND circuits 13-3 to 13-5 and the multiplexer 14 has inverters 14-1 and 14-2 and NAND circuits 14-3 to 14-5.
The delay circuit 11 is constituted so as to output a signal CLK having a base frequency from the outside by delaying the signal CLK by one unit time. The delay circuit 12 has a delay time two times larger than that of the delay circuit 11 and is constituted so as to output the signal CLK by delaying it by two unit times.
The multiplexer 13 always selects an output of the delay circuit 11 and outputs the output as a reference signal REF. Moreover, the multiplexer 13 is used to absorb the time required for the processing of the multiplexer 14 and synchronize with an output of the multiplexer 14. Therefore, when the processing of the multiplexer 14 is very fast and the processing time can be ignored, it is possible to directly output an output of the delay circuit 11 as the reference signal REF without using the multiplexer 13.
The multiplexer 14 selects the signal CLK or a signal sent from the delay circuit 12 in accordance with input data DIN and outputs it as transmission data (phase modulation signal) DATA. Specifically, the multiplexer 14 inputs the signal CLK and a signal (signal whose phase is delayed by two unit times from the signal CLK) sent from the delay circuit 12. Then, as shown in FIG. 10A, when the data DIN is “0”, the multiplexer 14 selects the signal CLK and outputs the signal CLK as transmission data DATA. When the data DIN is “1”, the multiplexer 14 selects a signal sent from the delay circuit 12 and outputs the signal as transmission data DATA. That is, the phase of the transmission data DATA output from the multiplexer 14 advances by one unit time tD1 from the phase of the reference signal REF output from the multiplexer 13 when the data DIN is equal to “0” and is output by being delayed by one unit time tD1 from the phase of the reference signal REF when the data DIN is equal to “1”. FIG. 10A is a timing chart showing operations of the data transmitter 1 in FIG. 7.
According to the above configuration, the reference signal REF and transmission data DATA are output from the data transmitter 1.
FIG. 9 is an illustration showing a configuration of the data receiver 2 in FIG. 7. As shown in FIG. 9, the data receiver 2 to which the reference signal REF and transmission data DATA are input has a phase comparator 21 and RS latch 22. The phase comparator 21 has inverters 21-1 to 21-6 and NAND circuits 21-7 to 21-15 and the RS latch 22 has NAND circuits 22-1 and 22-2.
The phase comparator 21 is constituted so as to input the reference signal REF and transmission data DATA and detect the phase difference between the reference signal REF and the transmission data DATA. Moreover, when the phase of the transmission data DATA advances from the phase of the reference signal REF, a phase advance detection signal R is output by having a pulse width equivalent to the phase difference. However, when the phase of the transmission data DATA delays from the phase of the reference signal REF, a phase delay detection signal S is output by having a pulse width equivalent to the phase difference.
That is, when the phase of the transmission data DATA advances from the phase of the reference signal REF by one unit time, the phase advance detection signal R is output by having a pulse width equivalent to one unit time. However, when the phase of the transmission data DATA delays from the phase of the reference signal REF by one unit time, the phase delay detection signal S is output by having a pulse width equivalent to one unit time.
The RS latch 22 receives the phase delay detection signal S and the phase advance detection signal R. As shown in FIG. 10B, the RS latch 22 obtains a demodulation output DOUT so that the demodulation output DOUT is set to “0” when the phase advance detection signal R is applied to the reset input of the RS latch 22, that is, when the phase of the transmission data DATA advances from the phase of the reference signal REF, and the demodulation output DOUT is set to “1” when the phase delay detection signal S is applied to the set input of the RS latch 22, that is, when the phase of the transmission data DATA delays from the phase of the reference signal REF. FIG. 10B is a timing chart showing operations of the data receiver 2 in FIG. 7.
In the case of the above data transmission system, as shown in FIG. 1A, it is necessary that the phase of the phase modulation signal DATA advances or delays from the reference signal REF in accordance with the value of the input data DIN.
However, when a skew between a reference signal and a phase modulation signal occurs due to the delay fluctuation of LSIs or transmission lines and the phase modulation signal DATA always advances independently of the value of the input data DIN from the reference signal REF as shown in FIG. 11B or the phase modulation signal DATA always delays independently of the value of the input data DIN from the reference signal REF as shown in FIG. 1C, there is a problem that the receiver malfunctions.